1. Field
Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to a method and apparatus for foreground and background bandwidth calibration for a phase-locked loop (PLL) device utilized in various electronic applications and apparatuses.
2. Background
A phase-locked loop (PLL) is an electronic system or a device that generates an output signal whose phase is related to a phase of an input signal. PLL devices are utilized in various electronic applications, including but not limited to computers and communications (e.g., wireless communications). PLLs are used to generate a stable frequency in multiples or in fractional multiples of an input frequency, which can be employed as a clock frequency in digital circuits such as microprocessors.